1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device on an SOI (silicon on insulator) substrate.
2. Description of the Background Art
A semiconductor device (hereinafter referred to as an SOI semiconductor device) formed on an SOI substrate is isolated by the technique of trench isolation filling up an isolation region with an oxide film. A method of fabricating an SOIMOS transistor which is isolated by trench isolation is now described with reference to FIGS. 29 to 38 successively showing steps of the method.
First, an SOI substrate formed by a silicon substrate 1, a buried oxide film 2 buried in this silicon substrate 1 and an SOI layer 3 formed on the buried oxide film 2 is prepared for forming a pad oxide film 4 of about 100 to 300 .ANG. in thickness on the SOI layer 3 by thermal oxidation and further forming a nitride film 6 of about 2000 .ANG. in thickness thereon by CVD, as shown in FIG. 29. Then, a resist film 101 is patterned on the nitride film 6 in a portion corresponding to an active region described later.
The SOI substrate may be formed by SIMOX (separation by implanted oxygen), wafer bonding or any other method.
Then, the resist film 101 is employed as a mask for selectively removing the nitride film 6 by anisotropic dry etching such as RIE (reactive ion etching), as shown in FIG. 30. Etching conditions for the nitride film 6 and the pad oxide film 4 are so approximate to each other that the pad oxide film 4 is also etched under the conditions for etching the nitride film 6. The selection ratio is about 1 to 2.
Then, an oxide film of about 500 .ANG. in thickness is formed on the overall surface by CVD employing TEOS (tetraethyl orthosilicate) and so anisotropically etched that this oxide film remains on side surfaces of the nitride film 6 and the pad oxide film 4 as side wall oxide films 7 in self alignment, thereby obtaining the structure shown in FIG. 31.
Then, the nitride film 6 and the side wall oxide films 7 are employed as masks for selectively removing the SOI layer 3 by anisotropic dry etching, as shown in FIG. 32.
Then, a deposition oxide film 8 having a thickness (e.g., about 5000 .ANG.) larger than the total thickness of the SOI layer 3, the pad oxide film 4 and the nitride film 6 is formed on the overall surface by CVD for covering the active region and isolation regions as shown in FIG. 33, and thereafter polished and planarized by CMP (chemical mechanical polishing) until exposing the nitride film 6. FIG. 33 shows an intermediate stage of the step of planarizing the deposition oxide film 8.
Then, the nitride film 6 is removed with phosphoric acid of about 160.degree. C. in temperature, for leaving the pad oxide film 4 and the side wall oxide films 7 in a state enclosed with the deposition oxide film 8 as shown in FIG. 34. Then, an impurity is injected into the SOI layer 3 through the pad oxide film 4 for channel injection (channel doping), and thereafter the pad oxide film 4 is removed with hydrofluoric acid. Referring to FIG. 34, the pad oxide film 4, the side wall oxide films 7 and the deposition oxide film 8 are simultaneously removed by the hydrofluoric acid as shown by arrows.
FIG. 35 shows the pad oxide film 4 not yet completely removed, and FIG. 36 shows the state after complete removal of the pad oxide film 4. As shown in FIG. 36, depression parts DP are formed on the deposition oxide film 8 in the vicinity of peripheral edge portions of the SOI layer 3. The side wall oxide films 7 which are TEOS oxide films are removed with the hydrofluoric acid faster than the pad oxide film 4 which is a thermal oxide film. Thus, the side wall oxide films 7 are removed before the pad oxide film 4 is completely removed, to facilitate removal of the deposition oxide film 8 on the portions provided with no side wall oxide films 7.
Then, a gate oxide film 9 of about 70 .ANG. in thickness is formed on the SOI layer 3, and thereafter a gate electrode 10 of about 2000 .ANG. in thickness is formed on the gate oxide film 9 and the deposition oxide film 8, as shown in FIG. 37.
Thereafter the patterned gate electrode 10 is employed as a mask for injecting an impurity into the SOI layer 3 and forming source/drain regions (not shown) in self alignment, parts of the gate oxide film 9 are removed except that located under the gate electrode 10, and an interlayer insulating film 11 is formed oh the overall surface. Contact holes CH are formed to reach the gate electrode 10 and the source/drain regions through the interlayer insulating film 11 and conductor layers are buried in the contact holes CH for forming wiring layers 12, thereby obtaining the SOI semiconductor device shown in FIG. 38.
However, the conventional SOI semiconductor device fabricated through the aforementioned steps has the following problems:
When the pad oxide film 4 formed on the SOI layer 3 is removed, the depression parts DP are disadvantageously formed on the deposition oxide film 8 in the vicinity of the peripheral edge portions of the SOI layer 3, as shown in FIG. 36. If the gate oxide film 9 and the gate electrode 10 are formed on the SOI layer 3 in this state, it comes to that the gate oxide film 9 and the gate electrode 10 are formed also on the depression parts DP.
FIG. 39 shows one of the depression parts DP in detail. As shown by arrows in FIG. 39, the part of the gate electrode 10 located in the depression part DP applies an electric field to the gate oxide film 9 on the peripheral edge portion of the SOI layer 3 in operation of the device, and hence the electric field strength on this part exceeds that on the part of the gate oxide film 9 located on the major surface of the SOI layer 3, to result in dielectric breakdown of the gate oxide film 9 and reduction of reliability thereof.
Due to electric field concentration, further, a channel is formed on the peripheral edge portion of the SOI layer 3 located under the gate electrode 10 with a lower voltage than that in the remaining portion of the SOI layer 3 to feed a current, and the MOS transistor may be partially turned on at the peripheral edge portion of the SOI layer 3. This MOS transistor is referred to as a parasitic MOS transistor. The parasitic MOS transistor may be turned on with a gate voltage not turning on the essential MOS transistor, to disadvantageously result in unnecessary power consumption.